The present invention relates to a three-level neutral-point-clamped PWM inverter apparatus which is one of a power converter such as an inverter or a servo drive that speed-variably drives a motor, and a power converter that interconnects systems, and also to a neutral voltage controller which is used in such a three-level neutral-point-clamped PWM inverter to control a neutral voltage that is a voltage between a neutral point of two capacitors connected in series between positive and negative busses of the apparatus, and the negative bus.
FIG. 1 is a circuit diagram showing the main circuit configuration of a three-level neutral-point-clamped PWM inverter apparatus. As shown in FIG. 1, the three-level neutral-point-clamped PWM inverter apparatus is configured by two capacitors 7, three-phase output terminals, twelve switching elements 8, and eighteen diodes 9.
In the thus configured three-level neutral-point-clamped PWM inverter apparatus, when switching elements 81, 82 are turned on, the output terminals of the phases are connected to a positive bus which is connected to a point P, and output phase voltages of the phases are at a high level. When switching elements 82, 83 are turned on, the output terminals of the phases are connected to a point C which is the neutral point, and the output phase voltages of the phases are at an intermediate level (neutral voltage) which is between the high level and a low level. When switching elements 83, 84 are turned on, the output terminals of the phases are connected to a negative bus which is connected to a point N, and the output phase voltages of the phases are at the low level. In the three-level neutral-point-clamped PWM inverter apparatus, usually, the switching elements 8 are switched on the basis of the above-mentioned three patterns to drive a three-phase load.
In such a three-level neutral-point-clamped PWM inverter apparatus, the neutral voltage is obtained by voltage division of the capacitors 7. The neutral voltage is varied in accordance with a current supplied to the load. When the neutral voltage is varied, an excess voltage is applied to the capacitors 7, thereby causing the possibility that the capacitors 7 are shortened in life or broken. In a three-level neutral-point-clamped PWM inverter apparatus, therefore, a neutral voltage control is performed in order to suppress or control variation of the neutral voltage.
In a neutral voltage control of the thus configured neutral-point-clamped PWM inverter, conventionally, the current flowing through the neutral line is controlled by using dipolar modulation or unipolar modulation as a method of generating PWM pulses, and increasing and decreasing the zero-sequence voltage of a voltage command.
On the other hand, as disclosed in JP-A-5-292754, when the concept of a voltage vector is introduced and a PWM control is performed, a method is usually employed in which a neutral voltage control is performed while the increasing or decreasing direction of an intermediate voltage vector is determined from the sign of a load power. As proposed in JP-A-2001-57784, such a method includes that in which a generation time ratio of a correction vector is finely adjusted in accordance with the direction of a current flowing through a neutral line.
In these methods, variation of the neutral voltage is suppressed by, among twelve sets of switch states such as shown in FIG. 2, adjusting the ratio of paired switch states in which the output voltages are equal to each other but the current directions of the neutral line are opposite to each other.
As proposed in JP-A-2001-61283, there is also a method such as shown in FIG. 3 in which a switch state disturbing the neutral voltage is suppressed. When switch states which can be attained by a neutral-point-clamped PWM inverter are indicated in the form of output voltage vectors, they can be expressed as shown in FIG. 4.
FIG. 5 shows an example of an apparatus which calculates a PWM pulse of a neutral-point-clamped PWM inverter with using the concept of a space voltage vector. The apparatus comprises a vector time calculator 102, a vector time register 103, a PWM pulse pattern setting device 104, and a parameter setting device 105.
In the apparatus, it is assumed that an output voltage output from the inverter is a space vector quantity such as shown in FIG. 4. When the modulation rate (k) and phase (xcex8) of an output voltage V are given, the vector time calculator 102 outputs the region of the output voltage vector V to the PWM pulse pattern setting device 104, selects the 27 kinds of vectors shown in FIG. 4, and calculates vector sequences which are sequentially output and vector output times (T0-T5) as PWM pulses in which an average of PWM periods is equal to the output voltage vector V. The vector sequences and the vector output times (T0-T5) are stored in the vector time register 103. The vector sequences and vector output times which are stored are converted by the PWM pulse pattern setting device 104 to a pulse sequence of U1, U2, V1, V2, W1, and W2 which drive switch elements of an inverter main circuit. The switch elements of the inverter main circuit are turned on/off by the pulse sequence, and a desired voltage is output. In this apparatus, on the basis of the neutral voltage from the parameter setting device 105 and a signal from a detector for a load power factor, the PWM pulse pattern setting device 104 adjusts the generation time of the correction vector in a direction along which the variation of the neutral voltage is reduced.
JP-A-9-37592 discloses a method of PWM controlling a three-level inverter in which a region between one long vector of output space vectors of a three-level inverter, and a vector that is adjacent to the long vector, and that has an intermediate length is set as one space. The whole space of 360xc2x0 which is formed by these vectors is divided into twelve regions. The region number of a command vector in the twelve regions is judged depending on the rotation angle of the command vector. The modulation rate is calculated in accordance with the degree of the command vector. The transmission system and the transmission sequence for suppressing variation of the neutral voltage of voltage dividing capacitors of the three-level inverter are determined in accordance with the modulation rate and the current ratio. Specific output times of the vectors in the transmission system and the transmission sequence are calculated to PWM control the three-level inverter.
As described above, in a three-phase neutral-point-clamped PWM inverter, usually, an even number of capacitors are directly connected between positive and negative busses of a main circuit in order to obtain the neutral voltage, and a neutral line is used while being taken out from a capacitor terminal which has a voltage that is exactly the middle voltage between the positive and negative busses. The neutral line is connected as shown in FIGS. 2 and 3 depending on the output load of the PWM inverter and the switch states of the PWM inverter. The voltage of the neutral line (the neutral voltage) is varied in accordance with the current which charges the capacitors through the positive and negative busses, and that which is supplied from the connected load.
As shown in the conventional art examples, in the switch states shown in FIG. 3 (in the description, the vector is referred to as a correction vector), a set of switch states in which the line voltage to be output to the load is the same but the phase of the load connected to the neutral line is different (adjacent switch states in FIG. 2 are bundled into one set) is used, and the time ratio in which the switch states of the set are generated is adjusted, whereby the neutral potential can be finely controlled.
In the switch states shown in FIG. 2 (in the description, the vector is referred to as an intermediate vector), however, the neutral voltage is varied by the phase currents of the load connected to the neutral line and the time ratio in which the switch state is generated, and there is no vector which corrects the variation. Therefore, the variation of the neutral voltage caused by an intermediate vector must be corrected with using a correction vector.
As shown in JP-A-2-261063, therefore, a zero-sequence voltage is added to the modulation rate, the occurrence time of a correction vector is adjusted, and the variation of the neutral voltage is controlled without changing the output line voltage which is to be supplied to a load. As shown in JP-A-5-292754 and JP-A-2001-57784, also in the method which uses the concept of a space voltage vector, an output is conducted so that a correction vector is used in a voltage vector to be used, and the occurrence time of the switch state of the set is adjusted to control the neutral voltage. In these methods, however, the technique of determining the ratio of the correction vector to make the neutral voltage variation close to zero is not optimum, and the effect of suppressing the neutral voltage variation is insufficient.
In the method described in JP-A-9-37592, the transmission system and the transmission sequence for suppressing variation of the neutral potential of the voltage dividing capacitors of the predetermined three-level inverter are determined in accordance with the modulation rate and the current ratio, and specific output times of the vectors in the transmission system and the transmission sequence are calculated to perform a PWM control. Therefore, it is possible to bring the neutral current close to zero. In the method also, however, the neutral voltage variation cannot be reduced completely to zero.
FIG. 6 is a block diagram showing the configuration of a conventional neutral voltage controller which detects the level of the neutral voltage and outputs a neutral voltage control command for suppressing the neutral voltage variation. As shown in FIG. 6, the conventional neutral voltage controller is configured by two isolation amplifiers 6 and a calculation circuit 3.
A first reference voltage Vref1 which is one half of a voltage VPN (DC bus voltage) between the point P and the point N, and a voltage between the point C and the point N, i.e., the neutral voltage VCN are input to the two isolation amplifiers 6, respectively. The calculation circuit 3 receives outputs of the two isolation amplifiers 6, calculates a neutral voltage control command for making the neutral voltage VCN and the first reference voltage Vref1 coincident with each other, and outputs the command. The neutral voltage control command is a command to produce an output pattern of a PWM (Pulse Width Modulation) command for raising or lowering the value of the neutral voltage.
As described above, in the neutral voltage controller, the neutral voltage VCN and the first reference voltage Vref1 are input to the calculation circuit 3, and hence the two isolation amplifiers 6 serving as insulation circuits are required. Such insulation circuits are required because the calculation circuit 3 is usually driven by a power source which is different from that for the main circuit of the inverter.
However, the isolation amplifiers 6 are expensive analog insulation circuits having a wide linear characteristic, and therefore have a problem in that the neutral voltage controller is expensive. In the conventional neutral voltage controller, since the calculation circuit 3 controls the neutral voltage on the basis of analog signals, there is a problem in that the apparatus is easily affected by noises or the like.
It is an object of the invention to provide a three-phase neutral-point-clamped PWM inverter apparatus in which the neutral potential variation can be efficiently suppressed, and the safety and the quality of the output voltage can be improved.
In order to attain the object, in the three-phase neutral-point-clamped PWM inverter apparatus of the invention, a first calculated value which is a product of: a calculated value of a time of three-phase output voltages in a state where a positive bus, a negative bus, and a neutral line are connected respectively to three-phase phase output terminals; and a predicted neutral current value in the state is obtained. Moreover, second and third calculated values which are products of: a calculated value of a time of the three-phase output voltages that can take state 1 where two of the three-phase phase output terminals are connected to the positive bus or the neutral line, and a remaining one terminal is connected to the neutral line or the negative bus, and state 2 opposite to the state; and predicted neutral current values in states 1 and 2 are obtained. Furthermore, on the basis of the first, second, and third calculated values, a time ratio of state 1 and 2 during a PWM period is determined so as to make a current flowing through the neutral line close to zero, or a potential of the neutral line of the three-phase output voltages close to a potential which is exactly the middle between voltages of the positive and negative busses.
According to the configuration, the neutral potential variation can be efficiently suppressed by making close to zero as far as possible, or making the potential of the neutral line close to a potential which is exactly the middle between the potentials of the positive and negative busses. Therefore, the safety and the quality of the output voltage can be improved.
It is another object of the invention to provide a neutral voltage controller which is economical, and highly reliable and accurate.
In order to attain the object, in the invention, a first reference voltage value which is one half of a voltage between a positive bus and a negative bus is subtracted from a value of a neutral voltage, when a result of the subtraction is smaller than a second reference voltage value which is a negative value, a signal for raising the neutral voltage is turned on, when the result of the subtraction is larger than a third reference voltage value which is a positive value, a signal for lowering the neutral voltage is turned on, the two signals are converted in an insulative manner to a 2-bit digital signal, and a neutral voltage control command is calculated on the basis of the digital signal and then output.
According to the configuration, the differences between the neutral voltage and the reference voltage values are expressed by a digital signal instead of an analog signal, thereby enabling economical insulating means to be used without using expensive insulating means having a wide linear characteristic. Therefore, the whole apparatus can be economically configured. Since the differences between the neutral voltage and the reference voltage values are processed in the form of a digital signal instead of an analog signal, an influence of noises on an input to calculating means can be reduced. Therefore, it is possible to provide a neutral voltage controller in which the reliability is enhanced, and which is highly accurate.